Intel Off Campus Placement 2021 Hiring Freshers As Technical Intern of Any Degree Graduate
Intel Off Campus Placement 2021: At Intel, we’re on a journey from a PC-centric company to a data-centric company. Our unmatched depth of experience and scope of vision allows us to dream big, to create a world where Intel powers the future of computing and communications—including powerful processors and accelerators that unlock the full potential of data. We continuously deliver advances in performance, power, and connectivity across a diversity of data-centric workloads, so our customers can harness the raw power of data.
Company Name: Intel
Website: Intel
Wikipedia: Intel Wiki
Job Profile: Intern
Degree Needed: B.E/B.Tech/M.E/M.Tech
Batch Eligible: 2018/2019/2020/2021
Work Location: Bangalore
Salary: Best In Industry
Jobs By Location And Passout Year:
| Pune | Hyderabad | Delhi |
| Mumbai | Coimbatore | Noida |
| Bangalore | Chennai | Off Campus |
| Nagpur | Gurgaon | Walk In |
| 2015 Batch | 2018 Batch | 2021 Batch |
| 2016 Batch | 2019 Batch | 2022 Batch |
| 2017 Batch | 2020 Batch | 2023 Batch |
Qualifications
- You should be a student (Post graduate/Masters – ME/MTech/MS) currently pursuing studies in relevant field with good understanding of semiconductor physics and basic PC computer architecture. Additional qualifications include:
- Familiarity with Very Large Scale Integration (VLSI) Complementary Metal-Oxide Semiconductor (CMOS) logic circuit design
- Well versed in UNIX*, C programming and relevant Computer Aided Design (CAD) tools
Job Description:
In this position, you will be involving in the training, design and development of next generation Server SOCs/CPUs. Your responsibilities will include some of the following but not limited to:
- Assist design unit owner in Register Transfer Level (RTL) modeling & functional validation. Use EDA tools extensively to simulate logic behavior and circuit performance and direction of physical design for next generation, deep sub-micron embedded circuit solutions. Verify the circuit behavior against the original simulation model and first silicon.
- Define VLSI Structural Design methodology and developing design flows. Implement structural physical designs, such as synthesis, floor planning, power-grid and clock tree designs, timing budgeting and closure, place and route, RC-extraction and integration. Verify structural physical designs, such as functional equivalency, timing/performance, noise, layout design rules, reliability and power
- Develop Analog IP on next generation deep submicron process for the Intel’s SOC, perform tasks related to Very-large-scale integration (VLSI) complementary metal-oxide-semiconductor (CMOS) IC design, Solid state physics and physical layout. Such tasks may include: Circuit design of high speed clocking related circuits [phase-locked loop (PLL), delay-locked loop (DLL), bandgap] or high voltage input/output (IO) [double data rate (DDR)/LPDDR, General-purpose input/output (GPIO), OPIO].
- Responsible for Integration of Third party IPs — Synthesis, functional and/or timing convergence, and pre and post-si debug of IPs developed by various external vendors as well as within the company. Handling of signals crossing power planes and clock domains, industry standard protocols including hardware and software details dealing with Memory (LPDDR), storage (eMMC, SATA, UFS), peripherals (PCIe, USB), and MIPI interfaces in SOC devices. System integration dealing with Si/ Platform/ FW/ MW/ drivers/ OS/ Apps on Android & Windows-based tablets and phones
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