GlobalFoundries Off Campus Drive 2021 Hiring Freshers As Intern of Any Degree Graduate

GlobalFoundries Off Campus Drive 2021 Hiring Freshers As Intern of Any Degree Graduate

GlobalFoundries Off Campus Drive 2021: GLOBALFOUNDRIES is an American semiconductor foundry headquartered in Santa Clara, California, United States. GLOBALFOUNDRIES was created by the divestiture of the manufacturing arm of Advanced Micro Devices.

Company Name: Global Foundries

Company Website: Global Foundries

Wikipedia: GlobalFoundries Wiki

Job Role: Intern

Degree Needed: B.E/B.Tech/M.E/M.Tech

Passout Year: 2018/2019/2020/2021

Work Location: Bangalore

Experience Level: 0 – 2 Years

Jobs By Location And Passout Year:

Qualifications:

• You should be a student (Post graduate/Masters – ME/MTech/MS) currently pursuing studies in relevant field with good understanding of semiconductor physics and basic PC computer architecture.

Additional qualifications include:

• Familiarity with Very Large Scale Integration (VLSI) Complementary Metal-Oxide Semiconductor (CMOSand Finfet ) logic circuit design
• Well versed in UNIX*, C programming and relevant Computer Aided Design (CAD) tools Inside TE ( technology enablement )  is a worldwide organization focused on the development and integration of SOCs, Test chips and Cores, and critical IPs( analog, RF, memories, std cells)  that power GF’s  Customer Products.
• This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting diffrentiating solutions for our customers.

Job Description for GLOBALFOUNDRIES Hiring Freshers:

• Responsibilities may be quite diverse of a technical nature.
• Experience and education requirements will vary significantly depending on the unique needs of the job.
• Job assignments are usually for the summer or for short periods during breaks from school for minimum of 6 months and max 11 months .

Your responsibilities will include some of the following but not limited to:

• Assist design unit owner in Register Transfer Level (RTL) modeling & functional validation.
• Use EDA tools extensively to simulate logic behavior and circuit performance and direction of physical design for next generation, deep sub-micron embedded circuit solutions.
• Verify the circuit behavior against the original simulation model and first silicon.
• Define VLSI Structural Design methodology and developing design flows.
• Implement structural physical designs, such as synthesis, floor planning, power-grid and clock tree designs, timing budgeting and closure, place and route, RC-extraction and integration.
• Verify structural physical designs, such as functional equivalency, timing/performance, noise, layout design rules, reliability and power.
• Develop Analog IP on next generation deep submicron process for the Global foundries customer SOCs, perform tasks related to Very-large-scale integration (VLSI) complementary metal-oxide-semiconductor (CMOS) IC design and FINFET based designs, Solid state physics and physical layout.
• Such tasks may include: Circuit design of high speed clocking related circuits [phase-locked loop (PLL), delay-locked loop (DLL), bandgap] or high voltage input/output (IO) , General-purpose input/output (GPIO), OPIO].
• Responsible for Integration of Third party IPs
• Synthesis, functional and/or timing convergence, and pre and post-si debug of IPs developed by various external vendors as well as within the Global foundries
• Handling of signals crossing power planes and clock domains, industry standard protocols including hardware and software details dealing with Embedded Memories .
• System integration dealing with Si/ Platform/ FW/ MW/ drivers/ OS/ Apps on Android & Windows-based systems .

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